One or more embodiments relate to a flash memory device and a method of fabricating the same, and more particularly, to a flash memory device and a method of fabricating the same, is capable of improving interference effect between neighbor cells and a cycling threshold voltage shift.
In a NAND type flash memory device, a plurality of cells for storing data is electrically connected to each other in series, thereby forming one cell string. A drain selection transistor is formed between the cell string and a drain, and a source selection transistor is formed between the cell string and a source. The cell of the NAND type flash memory device is formed by forming gates on certain areas of a semiconductor substrate and then forming junctions on both sides of each of the gates. The gate has a stack structure of a tunnel insulating layer, a floating gate, a dielectric layer, and a control gate.
In the above NAND type flash memory device, the state of the cell is influenced by the operations of the neighbor cells, and so it is important to maintain constantly the state of the cell. A change in the state of the cell resulting from operations (in particular, the program operation of neighbor cells) is called an “interference effect.” In other words, the interference effect refers to a phenomenon where, when a first cell to be read is read, a threshold voltage higher than that of the first cell is read because of the effect of capacitance resulting from a change in the charges of the floating gate of a second cell when the second cell adjacent to the first cell is programmed. The interference effect also refers to a phenomenon where, although the charges of the floating gate of a cell being read is not changed, the state of the cell seems to be distorted by a change in the states of neighbor cells. The state of a cell is changed because of the interference effect, which results in an increase in the ratio of faulty devices and a decrease in the production yield. Accordingly, in order to constantly maintain the state of a cell, it is useful to minimize the interference effect.
As the integration degree of semiconductor devices increases, the distance between the floating gates decreases, and the interference becomes an important factor. Accordingly, attempts have been made to reduce the interference. For example, it was proposed a method of forming an isolation layer 17 having a wing spacer W formed on the sidewalls of a tunnel oxide layer 13 on a semiconductor substrate 11, as shown in FIG. 1, instead of forming a flat-shaped dielectric layer. A dielectric layer 19 and a control gate 21 are formed over the isolation layer 17.
This wing spacer W is formed by lowering the Effective Field Oxide Height (EFH) at the central portion of a top surface of the isolation layer 17 than the height of the isolation layer 17 formed on the sidewalls of the tunnel oxide layer 13. The top surface of the isolation layer 17 is configured to have a U shape through the formation of the wing spacer W. Accordingly, the surface of the dielectric layer 19 formed over the isolation layer 17 will have a U shape, and the control gate 21 formed over the dielectric layer 19 having the U shape is formed deep between the floating gates 15. As described above, the control gate 21 formed between the floating gates 15 could improve the interference effect.
However, if the EFH at the central portion of the top surface of the isolation layer 17 is lowered as described above, a distance between the tunnel oxide layer 13 and the control gate 21 is reduced. Accordingly, the properties of the tunnel oxide layer 13 may be deteriorated because a cycling Vt shift of the tunnel oxide layer 13 is increased.
Meanwhile, if the distance between the wing spacers W of the isolation layer 17 decreases because the distance between the floating gates 15 decreases due to the high integration of devices, the dielectric layer 19 may fill the distance between the wing spacer W. Consequently, it is very difficult to improve the interference effect because, as the control gate 21 is formed deep between the floating gates 15, the bottom of the control gate 21 cannot be lowered.